URI researchers develop tool to simulate future computer chip performance
Todd McLeish, 401-874-7892
KINGSTON, R.I. – May 21, 2012 – Today’s computer chips typically operate with four to eight processors working together, but future chips are likely to use hundreds. That rapid increase in complexity is making it difficult for computer hardware engineers to predict how the computer of the future will behave.
“The tools we use to predict the behavior of large multi-core systems are very limited,” said Resit Sendag, University of Rhode Island professor of computer engineering. “Current practice is to use software simulators to model multi-core systems, but these simulators are thousands of times slower than the systems they model.”
Sendag and URI graduate student Will Simoneau have addressed this need for new tools to simulate chip performance by using Field Programmable Gate Arrays, which enable users to combine a wide variety of components to build any type of hardware configuration needed.
“Our prototype is easier to use than what else is available, it’s fully open source, and it’s already online for others to use,” said Simoneau, a resident of Wakefield. “The source code is smaller than most other similar projects, which means there is less to understand, and the hardware it generates is faster.”
Simoneau, who earned a bachelor’s degree from URI in computer engineering in 2008 at age 18 and was the youngest to be awarded a master’s degree from URI in 2011, describes the tool as “a computer code description of hardware, written in such a way that you can alter the design, then build it on any suitable FPGA chip within the family. You can build a small one-processor system with small caches, large multi-processor systems with large caches, or anything in between.”
The platform URI researchers developed is designed to be used primarily by the computer architecture research community and others interested in operating system research. It is also useful to those seeking to debug software programs.
Simoneau and Sendag presented a paper about the platform at the IEEE International Symposium on Performance Analysis of Systems and Software in April, where it was met with enthusiasm.
“I built it using a low-end circuit board that cost about $300, which means that just about anyone can download this tool right now and be able to start using it,” Simoneau said. “People were impressed with the performance we’re getting from my low-end board versus what others are trying to do with their high performance boards.”
What is somewhat surprising is that Simoneau and Sendag have released the platform as open source for anyone to download and use for free.
“There aren’t a lot of people who just give away their work, especially when you’ve spent years working on it,” Sendag said. “But we really believe in open source, and we know that people will appreciate that it’s available.”
The code can be found at www.ele.uri.edu/research/z4800
The URI scientists plan to present their new platform at meetings with Intel and IBM in coming weeks, with the hope that they may support future developments.
“We have lots more ideas on how to extend this to different models, and we think that industry will be very interested in those ideas,” Sendag said.